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(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 1/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa dram 1m x 16 dram edo page mode features y x16 organization y edo (extended data-out) access mode y 2 cas byte/word read/write operation y single power supply : 5v 10% vcc for 5v product 3.3v 10% vcc for 3.3v product y interface for inputs and outputs ttl-compatible for 5v products lvttl-compatible for 3.3v products y 1024-cycle refresh in 16ms y refresh modes : ras only, cas before ras (cbr) and hidden capabilities, y optional self-refresh capabilities(s-ver. only) y jedec standard pinout y key ac parameter t rac t cac t rc t pc -45 45 11 77 16 -5050138420 -60 60 15 104 25 ordering information - package 42-pin 400mil soj 44 / 50-pin 400mil tsop (typeii) product no. refresh vcc packing type m11b16161a-45j/50j/60j normal M11B16161SA-45j/50j/60j * self- refresh 5v m11l16161a-45j/50j/60j normal m11l16161sa-45j/50j/60j self- refresh 3.3v soj m11b16161a-45t/50t/60t normal M11B16161SA-45t/50t/60t *self- refresh 5v m11l16161a-45t/50t/60t normal m11l16161sa-45t/50t/60t self- refresh 3.3v tsopii * ordered by special request general description the m11b16161/m11l16161 series is a randomly accessed solid state memory, organized as 1,048,576 x 16 bits device. it offers extended data-output access mode. single power supply (5v 10%, 3.3v 10%), access time (-45,-50,-60), self- refresh function and package type (soj, tsop ii) are optional features of this family. all these family have cas - before - ras , ras -only refresh and hidden refresh. two access modes are supported by this device : byte access and word access. use only one of the two cas and leave the other staying high will result in a byte access. word access happens when two cas ( casl , cash ) are used. casl transiting low during read or write cycle will output or input data into the lower byte (io0~io7), and cash transiting low will output or input data into the upper byte (io8~15). pin assignment soj top view tsop (typeii) top view 1 2 3 4 5 6 7 8 9 v cc i/o0 i/o1 i/o2 i/o3 v cc i/o4 i/o5 i/o6 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 v ss i/o15 i/o14 i/o13 i/o12 v ss i/o11 i/o10 i/o9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 i/o7 nc nc we ras nc nc a0 a1 a2 a3 v cc 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 i/o8 nc casl cash oe a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 v cc i/o0 i/o1 i/o2 i/o3 v cc i/o4 i/o5 i/o6 i/o7 nc nc nc we ras nc nc a0 a1 a2 a3 v cc v ss i/o15 i/o14 i/o13 i/o12 v ss i/o11 i/o10 i/o9 i/o8 nc nc casl cash oe a9 a8 a7 a6 a5 a4 v ss 12 13 14 15 16 17 18 19 20 21 22 44 4 3 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 2/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa functional block diagram pin descriptions pin no. (soj package) pin name type description 17~20, 23~28 a0~a9 input address input row address : a0~a9 column address : a0~a9 14 ras input row address strobe 30 cash input column address strobe / upper byte control 31 casl input column address strobe / lower byte control 13 we input write enable 29 oe input output enable 2~5,7~10,33~36,38~41 i/o0 ~ i/o15 input / output data input / output 1,6,21 v cc supply power, (5v or 3.3v) 22,37,42 v ss ground ground 11,12,15,16,32 nc - no connect control logic data-in buffer clock generator data-out buffer column address buffer refresh controler refresh counter row . address buffers(10) a0 a1 a2 a3 a4 a5 a6 a7 column decoder oe 16 row decoder 1024 x 1024 x 16 memory array 16 sense amplifiers i/o gating 8 1024 x 16 v cc v ss io0 : io15 ras cash 1024 1024 10 10 10 10 casl v bb generator we 16 a8 a9 10
(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 3/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa absolute maximum ratings voltage on any pin relative to vss 5v product -1v to +7v 3.3v product -0.5v to +4.6v operating temperature, t a (ambient) .0 c to +70 c storage temperature (plastic) .-55 c to +150 c power dissipation 1.0w short circuit output current 50ma permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only, and functional operation of the device above those conditions indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and recommended operating conditions (0 c t a 70 c ) 3.3v 5v parameter conditions symbol min max min max units notes supply voltage v cc 3.0 3.6 4.5 5.5 v 1 supply voltage v ss 0000v input high voltage v ih 2.0 v cc +0.3 2.4 v cc +0.3 v 1 input low voltage v il -1.0 0.8 -1.0 0.8 v 1 input leakage current 0v v in v ih(max) i li -10 10 -10 10 m a output leakage current 0v v out v cc output(s) disable i lo -10 10 -10 10 m a 5v i oh = -5 ma output high voltage 3.3v i oh = -2 ma v oh 2.4 - 2.4 - v 5v i ol = 4.2 ma output low voltage 3.3v i ol = 2 ma v ol - 0.4 - 0.4 v note : 1.all voltages referenced to v ss max parameter conditions symbol -45 -50 -60 units notes operating current ras , cas cycling , t rc =min i cc1 150 140 130 ma 1,2 ttl interface , ras , cas = v ih , d out =high-z 444ma standby current cmos interface, ras , cas 3 v cc -0.2v i cc2 222 ma ras only refresh current t rc = min i cc3 150 140 130 ma 2 edo page mode current t pc = min i cc4 150 140 130 ma 1,3 cas before ras refresh current t rc = min i cc6 150 140 130 ma battery backup current (s-ver. only) standby with cbr refresh, t rc = 62.4us t ras 300ns, d out =hi-z, cmos interface i cc7 500 500 500 m a self refresh current (s-ver. only) ras , cas 0.2v, d out =hi-z, cmos interface i cc8 500 500 500 m a note : 1. i cc max is specified at the output open condition. 2. address can be changed twice or less while ras =v il . 3. address can be changed once or less while cas =v ih .
(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 4/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa capacitance (ta = 25 c , v cc = 5v 10% or 3.3v 10%) parameter symbol typ max unit input capacitance (address) c i1 -5pf input capacitance ( ras , cash , casl , we , oe ) c i2 -7pf output capacitance (i/o0~i/o15) c i / o -10pf ac electrical characteristics (ta = 0 to 70 c , v cc =5v 10% or 3.3v 10%, v ss = 0v) (note 14) test conditions input timing reference levels : 0.8v, 2.4v (for 5v power supply), 0.8v, 2.0v (for 3.3v power supply) output reference level : v ol = 0.8v, v oh =2.0v output load : 2ttl gate + cl (50pf) assumed t t = 2ns -45 -50 -60 parameter symbol min max min max min max unit notes read or write cycle time t rc 77 84 104 ns read write cycle time t rwc 97 110 135 ns edo-page-mode read or write cycle time t pc 16 20 25 ns 22 edo-page-mode read-write cycle time t pcm 53 58 68 ns 22 access time from ras t rac 45 50 60 ns 4 access time from cas t cac 11 13 15 ns 5,20 access time from oe t oac 11 13 15 ns 13,20 access time from column address t aa 22 25 30 ns access time from cas precharge t acp 25 28 33 ns 20 ras pulse width t ras 45 10,000 50 10,000 60 10,000 ns ras pulse width (edo page mode) t rasc 45 100,000 50 100,000 60 100,000 ns ras hold time t rsh 6 7 10 ns 25 ras precharge time t rp 28 30 40 ns cas pulse width t cas 6 10,000 7 10,000 10 10,000 ns 24 cas hold time t csh 35 37 40 ns 19 cas precharge time t cp 6 7 10 ns 6,23 ras to cas delay time t rcd 10 34 11 37 14 45 ns 7,18 cas to ras precharge time t crp 555ns19 row address setup time t asr 000ns row address hold time t rah 6 7 10 ns ras to column address delay time t rad 8239251230ns8 column address setup time t asc 000ns18 column address hold time t cah 6 7 10 ns 18 column address hold time (reference to ras ) t ar 40 44 55 ns column address to ras lead time t ral 23 25 30 ns column address setup to cas precharge t ach 10 11 13 ns
(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 5/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa (continued) -45 -50 -60 unit notes parameter symbol min max min max min max read command setup time t rcs 0 0 0 ns 15,18 read command hold time reference to cas t rch 000ns9,15,19 read command hold time reference to ras t rrh 000ns9 cas to output in low-z t clz 000ns20 output buffer turn-off delay from cas or ras t off1 0 11 0 13 0 15 ns 10,17,20 output buffer turn-off to oe t off2 0 11 0 13 0 15 ns 17,26 write command setup time t wcs 0 0 0 ns 11,15,18 write command hold time t wch 6 7 10 ns 15,25 write command hold time(reference to ras ) t wcr 40 44 55 ns 15 write command pulse width t wp 6 7 10 ns 15 write command to ras lead time t rwl 11 13 15 ns 15 write command to cas lead time t cwl 6 7 10 ns 15,19 data-in setup time t ds 0 0 0 ns 12,20 data-in hold time t dh 6 7 10 ns 12,20 data-in hold time (reference to ras ) t dhr 40 44 55 ns ras to we delay time t rwd 57 67 79 ns 11 column address to we delay time t aw d 34 42 49 ns 11 cas to we delay time t cwd 23 30 34 ns 11,18 transition time (rise or fall) t t 1 50 1 50 1 50 ns 2,3 refresh period (1024 cycles) t ref 16 16 16 ms refresh period (1024 cycles) self refresh t ref 64 64 64 ms ras to cas precharge time t rpc 555ns cas setup time(cbr refresh) t csr 555ns1,18 cas hold time(cbr refresh) t chr 10 10 10 ns 1,19 oe hold time from we during read-mode-write cycle t oeh 6 7 10 ns 16 oe low to cas high setup time t oes 555ns oe high hold time from cas high t oehc 222ns oe precharge time t oep 222ns oe setup prior to ras during hidden refresh cycle t ord 000ns last cas going low to first cas returning high t clch 6 7 10 ns 21 data output hold after cas returning low t coh 333ns output disable delay from we t whz 011013015ns self refresh ras low pulse width t rass 100 100 100 us 27,28 self refresh ras high precharge time t rps 77 84 104 ns 27,28 self refresh cas hold time t chs -50 -50 -50 ns 27,28 read setup time reference to ras in cbr/sr t rsr 0 0 0 ns 27,28 read hold time reference to ras in cbr/sr t rhr 6 7 10 ns 27,28
(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 6/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa notes : 1. enables on-chip refresh and address counters. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il . 3. in addition to meet the transition rate specification, all input signals must transit between v ih and v il in a monotonic manner. 4. assume that t rcd < t rcd (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will increase by the amount that t rcd exceeds the value shown. 5. assume that t rcd 3 t rcd (max) 6. if cas is low at the falling edge of ras , data-out will be maintained from the previous cycle. to initiate a new cycle and clear the data-out buffer, cas and ras must be pulsed high. 7. operation within the t rcd limit ensures that t rcd (max) can be met, t rcd (max) is specified as a reference point only ; if t rcd is greater than the specified t rcd (max) limit, access time is controlled by t cac . 8. operation within the t rad limit ensures that t rad (max) can be met. t rad (max) is specified as a reference point only ; if t rad is greater than the specified t rad (max) limit, access time is controlled by t aa . 9. either t rch or t rrh must be satisfied for a read cycle. 10. t off1 (max) defines the time at which the output achieves the open circuit condition ; it is not a reference to v oh or v ol . 11. t wcs , t rw d , t aw d and t cw d are restrictive operating parameters in late write and read-modify- write cycle only. if t wcs 3 t wcs(min) , the cycle is an early write cycle and the data output will remain an open circuit throughout the entire cycle. if t rw d 3 t rwd(min) , t aw d 3 tawd(min) and t cwd 3 t cwd(min) , the cycle is read-write and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of i/o (at access time and until cas and ras or oe go back to v ih ) is indeterminate. oe held high and we taken low after cas goes low result in a late write ( oe -controlled) cycle. 12. those parameters are referenced to cas leading edge in early write cycles and we leading edge in late write or read-modify- write cycles. 13. during a read cycle, if oe is low then taken high before cas goes high, i/o goes open, if oe is tied permanently low, a late write or read-modify- write operation is not possible. 14. an initial pause of 200 m s is required after power-up followed by eight ras refresh cycles ( ras only or cbr) before proper device operation is assured. the eight ras cycle wake-ups should be repeated any time the t ref refresh requirement is exceeded. 15. write command is defined as we going low. 16. late write and read-modify-write cycles must have both toff2 and t oeh met ( oe high during write cycle) in order to ensure that the output buffers will be open during the write cycles. 17. the i/os open during read cycles once t off1 or t off2 occur. 18. referenced to the earlier cas falling edge. 19. referenced to the latter cas rising edge. 20. output parameter (i/o) is referenced to corresponding cas input, io0~7 by casl and io8~15 by cash . 21. last falling cas edge to first rising cas edge. 22. last rising cas edge to next cycle?s last rising cas edge. 23. last rising cas edge to first falling cas edge. 24. each cas must meet minimum pulse width. 25. referenced to the latter cas falling edge. 26. all ios controlled by oe , regardless casl and cash . 27. self refresh mode is initiated by performing a cbr refresh cycle and holding ras low for the specified t rass . self refresh mode is terminated by rising ras high for a minimum time of t rps . 28. for all of the refresh mode except the distributed cbr refresh mode, all rows must be refreshed within the refresh rate before and after self refresh.
(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 7/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa truth table addresses function ras casl cash we oe row col dq s notes standby h h ? xh ? x x x x x high-z read : word l l l h l row col data-out read : lower byte l l h h l row col lower byte, data-out read : upper byte l h l h l row col upper byte, data-out write : word (early write) l l l l x row col data-in write : lower byte (early) l l h l x row col lower byte, data-in , upper byte, high-z write : upper byte (early) l h l l x row col lower byte, high-z , upper byte, data-in read-write l l l h ? ll ? h row col data-out, data-in 1, 2 1st cycle l h ? lh ? l h l row col data-out 2 2nd cycle l h ? lh ? lh l coldata-out 2 edo-page-mode read any cycle l l ? hl ? h h l data-out 2 1st cycle l h ? lh ? l l x row col data-in 1 edo-page-mode write 2nd cycle l h ? lh ? ll x coldata-in 1 1st cycle l h ? lh ? lh ? ll ? h row col data-out, data-in 1, 2 edo-page-mode read-write 2nd cycle l h ? lh ? lh ? ll ? h col data-out, data-in 1, 2 hidden refresh l ? h ? l l l h l row col data-out 2 ras -only refresh l h h x x row high-z cbr refresh h ? l l l h x x x high-z 3 *note : 1. these write cycles may also be byte write cycles (either casl or cash active). 2. these read cycles may also be byte read cycles (either casl or cash active). 3. only one cas must be active ( casl or cash ).
(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 8/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa read cycle note: 1. t off1 is referenced from the rising edge of ras or cas , whichever occurs last. ras v ih v il casl,cash v ih v il v ih v il addr v ih v il we v oh v ol i/o v ih v il oe t rc t ras t rp row column valid data row t crp t csh t rsh t cas t clch t rr h open open t off2 t oac t clz t cac t rcs t rac t aa t off1 note1 t asr t rah t asc t cah t rad t ral t ar t rcd t rch valid data ras casl,cash addr t rc t ras t rp row column row t crp t csh t rsh t cas t clch t cwl t wp t wch t asr t rah t as c t cah t rad t ral t ar t rcd t rwl t wcr t wcs t dh t ds t dhr we oe don't care undefined v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il i/o t ach t ach early write cycle
(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 9/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa *note : 1. t off1 is referenced from the rising edge of ras or cas , whichever occurs last. 2. t pc can be measured from falling edge of cas to falling edge of cas , or from rising edge of cas to rising edge of cas . both measurements must meet the t pc specification. ras v ih v il casl,cash v ih v il v ih v il addr v ih v il we v i/oh v i/ol i/o v ih v il oe t rwc t ras t rp row column row t crp t csh t rsh t cas, t clch open t dh t off2 t clz t cac t rcs t rac t aa t as r t rah t as c t cah t rad t ral t ar t rcd t cwl ras casl,cash addr t rp row t crp t cp t cas, t clch t rah t as c t cah t rad t ar t rcd we oe don't care undefined v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il i/o t rwl t wp t awd t rwd t cwd val id d out t ds t oeh t oac row t asr t cah t as c t cah t as c t csh column t cp t pc (note2) column t ral t cas, t clch t rsh t cp column t rcs t rrh t rch valid data valid data t cac t clz t rac t aa t cac t coh t acp t aa t cac t clz t acp t aa valid data open note1 t of f1 open t oac t oes t off2 t oehc t oac t oes t oep t off2 t rasc valid d in t cas, t clch t ach t ach t ach t ach read write cycle ( late write and read-modify-write cycles ) edo-page-mode read cycle
(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 10/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa edo-page-mode early-write cycle note : 1. t pc can be measured from falling edge to falling edge of cas , or from rising edge to rising edge of cas . both measurements must meet the t pc specification. ras v ih v il casl,cash v ih v il v ih v il addr v ih v il we v ih v il i/o v ih v il oe t rasc t rp t crp t ds t wcs t dhr t wcr t asr t rah t asc t cah t rad t ar t cwl ras casl,cash addr we oe don't care undefined v ih v il v ih v il v ih v il v ih v il v i/oh v i/ol v ih v il i/o t wch t wp t wp t cwl t wch column row t cp t cas, t clch t rcd t csh t cas, t clch t cp t pc (note1) t cas, t clch t cp t rsh t asc t cah column t asc t cah column t ral row t wcs t wp t cwl t wch t wcs valid data t dh t ds t dh t ds t dh t rwl t rasc t rp t crp t rcs t asr t rah t as c t cah t rad t ar t cwd t rwd t awd t cas, t clch t rcd t csh t cas, t clch t cp t pcm t cas, t clch t cp t rsh t as c t cah t asc t cah t ral t cp row t cwl t wp t cwd t awd t cwl t wp t cwd t awd t cwl t wp t rwl t cl z t cac t ds t dh valid d out va lid d in t rac t aa valid d out valid d in t clz t cac t ds t dh t aa t acp t aa t acp t clz t cac t ds t dh valid d out t oac t oac t off2 t oac t off2 t oeh va lid d in t off2 valid data valid data column column column row t ach t ach t ach edo-page-mode read-write cycle (late write and read-modify-write cycles)
(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 11/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa edo-page-mode read-early-write cycle (psuedo read-modify-write) ras v ih v il v ih v il v ih v il addr v ih v il we v i/oh v i/ol i/o v ih v il oe ras casl,cash addr don't care undefined v ih v il v ih v il v ih v il v oh v ol i/o t rp row t crp t cp t cas t pc t rah t asc t cah t rad t ar t rcd row t asr t cah t asc t cah t asc t csh column(b) t cp t cas t cp column(n) t ral t cas t cp column(a) t rcs t rch t wcs valid data(b) t cac t rac t aa t cac t asr t aa t whz open t oac t ds t rasc t wch valid data in valid data(a) t coh t dh t rsh t ras t rc t rpc t crp row row t rah open t acp t rp casl,cash t ach ras only refresh cycle (addr = a0~a9 ; oe , we = dont care)
(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 12/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa cbr refresh cycle (a0~a9 ; oe = dont care) note : 1. t off1 is reference from the rising edge of ras or cas , whichever occurs last. ras v ih v il casl, cash v ih v il v ih v il we i/o ras casl,cash addr v ih v il v ih v il v ih v il v oh v ol i/o t rpc t rp (read) t ras t rp (refresh) t ras t chr t rsr t rhr t cp t rch t csr t rsr t rhr t csr t chr t rpc t rp t chr t ras open t rsh t crp t rc d row column t asr t rah t as c t rad t cah t ral t ar valid data open open t aa t rac t cac t clz note1 t off1 v ih v il oe t oac t ord t off2 don't care undefined t ras hidden refresh cycle ( we = high ; oe = low)
(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 13/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa self refresh cycle ( oe = dont care) ras casl,cash addr v ih v il v ih v il v ih v il v oh v ol i/o t chs open t rp t rass t rps we v ih v il t cp t csr t rpc t rsr t rch t rhr t rp c t crp t asr don't care undefined
(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 14/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa packing dimensions 42-lead soj(400mil) dimension mm dimension inch symbol min nom max min nom max a 3.35 3.51 3.68 0.132 0.138 0.145 a1 2.24 - - 0.088 - - a2 0.635 - - 0.025 - - b 0.41 0.46 0.51 0.016 0.018 0.020 b1 0.46 0.41 0.38 0.018 0.016 0.015 b2 0.66 0.71 0.81 0.026 0.028 0.032 c 0.18 0.20 0.28 0.007 0.008 0.011 c1 0.28 0.20 0.17 0.011 0.008 0.007 d 27.18 27.31 27.43 1.070 1.075 1.080 zd 1.09 ref 0.043 ref e 11.05 11.18 11.30 0.435 0.440 0.445 e1 10.03 10.06 10.29 0.395 0.400 0.405 e2 9.40 basic 0.370 basic ? 0 10 0 10 e 1.27 basic 0.050 basic
(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 15/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa packing dimensions 44 / 50-lead tsop(ii) dram(400mil) o l gage plane detail "a" section b-b metal base with plating 0.10 -c- d e e 1 e plane seating c 1 l 122 23 44 a 2 a b detail a -c- -c- b b c c 1 1 a 1 b-b dimension in mm dimension in inch symbol min nom max min nom max a - - 1.20 - - 0.047 a1 0.05 0.10 0.15 0.002 0.004 0.006 a2 0.95 1.00 1.05 0.037 0.039 0.041 b 0.30 - 0.45 0.012 - 0.018 b1 0.30 0.35 0.40 0.012 0.014 0.016 c 0.12 - 0.21 0.005 - 0.008 c1 0.10 0.127 0.16 0.004 0.005 0.006 d 20.82 20.95 21.08 0.820 0.825 0.830 e 11.56 11.76 11.96 0.455 0.463 0.471 e1 10.03 10.16 10.29 0.394 0.400 0.405 l 0.40 0.50 0.60 0.016 0.020 0.024 l1 0.80 ref 0.031 ref e 0.80 bsc 0.031 bsc q 0-80-8
(607 elite semiconductor memory technology inc. publication date : may. 2001 revision : 1.3 16/16 m11b16161a / M11B16161SA m11l16161a / m11l16161sa important notice all rights reserved. no part of this document may be reproduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. the information contained herein is presented only as a guide or examples for the application of our products. no responsibility is assumed by esmt for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. no license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of esmt or others. any semiconductor devices may have inherently a certain rate of failure. to minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.

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